In recent years, it has become possible to integrate several millions of transistors in one chip, as semiconductor fine-patterning techniques have progressed. As one of test methods for such semiconductor integrated circuit, there is a scan test that ensures an extremely high rate of fault detection.
FIG. 18 is a block diagram illustrating a conventional scan test circuit. In FIG. 18, the scan test circuit comprises external input terminals 111, 112, and 114, a combination circuit 118, normal data lines 119˜121, an external output terminal 124, and a scan chain having n (n>1) pieces of scan storage elements. The scan test circuit shown in FIG. 18 has three (n=3) scan storage elements 125˜127. Further, the scan test circuit has an output data line 122 of the scan storage element 125, and an output data line 123 of the scan storage element 126.
The external input terminal 111 receives a scan selection external signal for switching between normal operation and scan operation. The external input terminal 112 receives scan-in data. The external input terminal 114 receives a test clock. The scan storage elements 125˜127 hold and output the data in synchronization with the rising edge of the test clock inputted to the external input terminal 114. The external output terminal 124 outputs the output data of the scan storage element 127. The combination circuit 118 receives the data from the output data lines 122 and 123, and outputs the data to the normal data lines 119˜121. The scan test circuit shown in FIG. 18 tests the combination circuit 118.
FIG. 19 is a circuit diagram illustrating a concrete example of the scan storage elements 125˜127. In FIG. 19, the scan storage element comprises a selector circuit 1, a scan selection signal input terminal 2, a normal data input terminal 3, a scan-in input terminal 4, a scan clock input terminal 5, a storage element 6, and an output terminal 7.
The normal data input terminal 3 receives normal data. The scan-in input terminal 4 receives scan-in data. The scan clock input terminal 5 receives a scan clock. The scan selection signal input terminal 2 receives a scan selection external signal that is described later. The selector circuit 1 receives the normal data, the scan-in data, and the scan selection external signal, and outputs the normal data when the scan selection external signal is “0”, or outputs the scan-in data when the scan selection external signal is “1”. The storage element 6 holds and outputs the output signal of the selector circuit 1 in synchronization with the rising edge of the scan clock inputted to the scan clock input terminal 5. The output terminal 7 outputs the signal that is outputted from the storage element 6, to the outside.
FIG. 20 is a time chart for explaining the operation of the scan test circuit constituted as described above. In FIG. 20, reference numerals 1200˜1204 denote scan-in data inputted to the external input terminal 112, numerals 1210˜1212, 1250 and 1251 denote normal data on the normal data line 119, numerals 1220˜1222, 1260 and 1261 denote normal data on the normal data line 120, numerals 1230˜1232, 1270 and 1271 denote normal data on the normal data line 121, numeral 1198 denotes initial data that is stored in the scan storage element 127 during scan operation, and numeral 1199 denotes initial data that is stored in the scan storage element 126 during scan operation. Further, reference numerals 350˜355 indicate event timings. Other reference numerals denote the waveforms of signals at the signal lines and external terminals corresponding to the reference numerals shown in FIG. 18.
Hereinafter, the operation of the scan test circuit will be described with reference to FIGS. 18˜20. When the scan selection external signal inputted to the external input terminal 111 is “0”, the scan storage elements 125˜127 are in the normal operation mode, and perform the normal operation. That is, these elements serve as normal storage elements. To be specific, in synchronization with the rising edge of the test clock inputted to the external input terminal 114, the scan storage element 125 holds and outputs the normal data supplied from the normal data line 119, the scan storage element 126 holds and outputs the normal data supplied from the normal data line 120, and the scan storage element 127 holds and outputs the normal data supplied from the normal data line 121.
When the scan selection external signal inputted to the external input terminal 111 is “1”, the scan storage elements 125˜127 are in the scan mode, and perform the scan operation. That is, these elements serve as storage elements performing scan operation. To be specific, in synchronization with the rising edge of the test clock inputted to the external input terminal 114, the scan storage element 125 holds and outputs the scan-in data inputted to the external input terminal 112, the scan storage element 126 holds and outputs the output data of the scan storage element 125, and the scan storage element 127 holds and outputs the output data of the scan storage element 126.
Since the scan selection external signal is “1” at the event timing 350, the scan storage elements 125˜127 are in the scan mode. In synchronization with the rising edge of the test clock, the scan storage element 125 holds and outputs the scan-in data 1201 inputted to the external input terminal 112, the scan storage element 126 holds and outputs the output data 1200 of the scan storage element 125, and the scan storage element 127 holds and outputs the output data 1199 of the scan storage element 126. The external output terminal 124 outputs the output data 1199 of the scan storage element 127.
Since the scan selection external signal is “1” at the event timing 351, the scan storage elements 125˜127 are in the scan mode. In synchronization with the rising edge of the test clock, the scan storage element 125 holds and outputs the scan-in data 1202 supplied from the external input terminal 112, the scan storage element 126 holds and outputs the output data 1201 of the scan storage element 125, and the scan storage element 127 holds and outputs the output data of the scan storage element 126. The external output terminal 124 outputs the output data 1200 of the scan storage element 127.
The scan selection external signal transits to “0” at the event timing 352, and the scan storage elements 125˜127 are switched into the normal operation mode.
At the event timing 353, in synchronization with the rising edge of the test clock, the scan storage element 125 holds and outputs the normal data 1212 supplied from the normal data line 119, the scan storage element 126 holds and outputs the normal data 1222 supplied from the normal data line 120, and the scan storage element 127 holds and outputs the normal data 1232 supplied from the normal data line 121. The external output terminal 124 outputs the output data 1232 of the scan storage element 127.
At the event timing 354, the scan selection external signal transits to “1”, and the scan storage elements 125˜127 are switched into the scan mode.
At the event timing 355, in synchronization with the rising edge of the test clock, the scan storage element 125 holds and outputs the scan-in data 1204 supplied from the external input terminal 112, the scan storage element 126 holds and outputs the output data 1212 of the scan storage element 125, and the scan storage element 127 holds and outputs the output data 1222 of the scan storage element 126. The external output terminal 124 outputs the output data 1222 of the scan storage element 127.
As described above, according to the conventional scan test circuit and scan test control method, in the scan test circuit having the scan chain including the n pieces of scan storage elements (n: integer, n>0), the scan-in data are set in the scan storage element 125˜127 in the scan mode, and the normal data outputted from the combination circuit 118 in the normal operation mode are stored in the scan storage elements 125˜127, respectively, and then the normal data stored in the scan storage elements 125˜127 in the scan mode are shifted-in and outputted to the outside through the external output terminal 124 (scan out) to be observed, thereby detecting a fault in the semiconductor integrated circuit (for example, refer to “Design of Testable Logic Circuit”, written by R. G. Bennett, translated by Akemi Harada).
In the conventional scan test circuit and scan test control method, the scan-in data and the scan selection signal must be directly input to the scan storage elements in the semiconductor integrated circuit from the outside of the semiconductor integrated circuit. Therefore, the rate of data flow is determined at the I/O of the semiconductor integrated circuit and, as the result, the scan test cannot be carried out at the normal operation speed. Accordingly, in a semiconductor integrated circuit that ensures a high-speed frequency, the conventional scan test circuit and scan test control method cannot detect a delay fault that depends on the frequency while they can detect a stuck-at fault that does not depend on the frequency.